3rd Digital India RISC-V Symposium begins at IIT Madras on August 1

The 3rd Digital India RISC-V (DIR-V) Symposium 2026 began at IIT Madras’s Research Park in Chennai on Saturday, August 1, and will run through August 2, 2026.

The two-day event is being organised jointly by IIT Madras, the Ministry of Electronics and Information Technology (MeitY) and RISC-V International, drawing policymakers, global technology experts, researchers, startups, investors, faculty and students.

The symposium’s theme this year, ‘Empowering Bharat’s Semiconductor Future,’ focuses on indigenous processor technologies, secure computing systems, hardware innovation, artificial intelligence and the growing RISC-V ecosystem.

Attendees can expect keynote addresses, technical sessions, panel discussions, hands-on workshops, technology demonstrations, exhibitions and startup showcases, alongside the DIR-V Grand Challenge Hackathon showcasing RISC-V-based projects from students and startups.

In-person registration closed on July 26, 2026, after the venue reached capacity, though the event is being streamed live on YouTube for anyone wanting to follow along without registering.

RISC-V, an open-standard instruction set architecture free of licensing fees, has become a central piece of India’s strategy to build homegrown chip design capacity and cut reliance on imported processors.

India’s semiconductor push has gathered pace over the past two years, with the government backing fabrication units, chip design centres and research programmes aimed at reducing reliance on imported processors.

IIT Madras Research Park, the venue for this year’s symposium, has emerged as a hub for deep-tech startups working on hardware, semiconductors and embedded systems in the country.

Previous editions of the DIR-V symposium have drawn participation from chip designers, academic researchers and government officials, reflecting the event’s role as a meeting point for India’s RISC-V ecosystem.

MeitY has separately backed the development of indigenous RISC-V-based processors under its Digital India programme, part of a broader effort to build chip design capability alongside manufacturing incentives.

The Chennai event follows two earlier editions of the DIR-V symposium, each of which expanded in scale as more startups, research institutions and global chip companies engaged with India’s RISC-V initiatives.

Photo by Tester051005, Wikimedia Commons, CC BY-SA 4.0